Job Title:  Senior Physical Design Engineer

Position Summary: This position will involve all phases of a design project, including specification and architectural design, physical implementation of complex ASIC designs using Cadence Flow. This role involves collaborating with cross-functional teams to ensure that the design meets performance, power, and area specifications. The candidate may be expected to interface with customers to communicate specifications, design status, technical details, etc.

Primary Responsibilities:

• Perform tasks such as floorplanning, placement, routing, and optimization to ensure efficient and effective chip layout.
• Convert RTL code into a gate-level netlist, ensuring the design meets area, power, and performance targets.
• Conduct static timing analysis (STA) to ensure the design meets timing requirements across all process, voltage, and temperature corners.
• Perform power analysis and optimization to achieve stringent power targets, including dynamic and leakage power reduction techniques.
• Ensure the design adheres to manufacturing rules and matches the schematic, resolving any discrepancies (DRC, LVS).
• Identify and resolve antenna violations to prevent damage during the manufacturing process.
• Prepare the design for tapeout, including final checks, documentation, and coordination with the fabrication team.
• Work closely with front-end design teams, verification teams, and EDA tool vendors to ensure seamless integration and functionality.
• Develop and maintain scripts to automate repetitive tasks, improving efficiency and consistency in the design process.
• Troubleshoot and resolve issues related to physical design, timing, and power, ensuring robust and reliable designs.
• Create and maintain detailed documentation of design processes, methodologies, and best practices.

• Participate in technical reviews with design team and customer.
• Able to work independently and collaborate with local technical lead.
• Work with test engineers to facilitate development of test hardware, test plans, and participate in block level bring-up and characterization efforts and results.

Position Requirements:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 4-7 years of hands-on experience with EDA tools for physical design, synthesis, timing analysis, and verification, with a strong understanding of the entire ASIC design flow.
• Proficiency in scripting languages such as Perl, Python, or Tcl for automation, with the ability to write and debug complex scripts.
• In-depth understanding of semiconductor manufacturing processes, design methodologies, and industry standards.
• Strong knowledge of digital design principles, including RTL design, synthesis, and verification.
• Excellent problem-solving abilities, with a keen eye for detail and a methodical approach to debugging and optimization.
• Effective communication skills, with the ability to collaborate with cross-functional teams and present technical information clearly.
• Ability to adapt to new tools, technologies, and methodologies, staying current with industry trends and advancements.
• Strong organizational skills, the ability to manage multiple tasks simultaneously, and a proactive approach to continuous improvement.

About Us: Forza Silicon is a Business Unit in the Materials Analysis Division of AMETEK, Inc. Forza’s history begins at the formation of the CMOS imaging industry where company co-founders, Barmak Mansoorian and Daniel Van Blerkom were a critical part of the Photobit team. Along with Photobit Co-founder, Dr. Eric Fossum, and many others, the team pioneered the development of CMOS imaging technology. Founded in 2001, Forza Silicon has established itself as an innovator and industry leader in the field of mixed-signal IC and CMOS imaging designs that have set the standard of the possible. Primarily through long standing customer relationships and partner referrals, Forza has grown to where today the company employs one of the industry’s largest and most experienced independent CMOS imaging engineering teams.  To learn more about Forza Silicon, please go to www.forzasilicon.com